1. Field of the Invention
The present invention relates to a solid-state image pickup device.
2. Description of the Related Art
As a pixel cell of a solid-state image pickup device becomes micro-miniaturized more, particularly in a CMOS (complementary metal-oxide semiconductor) sensor (CMOS type solid-state image pickup device), it is frequently observed that a pixel portion also uses a trench element isolation structure (so-called STI: shallow trench isolation) structure similarly to a peripheral circuit portion.
Also, it becomes customary that a light-receiving portion uses a buried photodiode structure to decrease a dark current.
Then, when the pixel portion uses the shallow trench isolation structure as described above, since a depletion layer extending from a light-receiving sensor portion reaches the side wall of the shallow trench isolation layer, there arises a problem, in which a dark current is generated at the SiO2/Si interface of the side surface of this shallow trench isolation layer. For this reason, it has been requested to suppress the occurrence of the dark current on the side surface of the shallow trench isolation layer.
Also, even when the pixel portion does not use the shallow trench isolation structure, in order to increase sensitivity of a solid-state image pickup device, it has been requested to decrease the occurrence of the dark current in the pixel portion as much as possible.
Accordingly, in the shallow trench isolation structure realized by a LOCOS (local oxidation of silicon) method, it has been considered so far to decrease a dark current in a pixel portion.
For example, there is proposed a method in which a P+ region is formed under or near a LOCOS trench isolation layer and an N-layer in a photoelectric conversion portion is formed deeper than the LOCOS trench isolation layer to thereby decrease a dark current (see cited patent reference 1).
Further, there is also proposed a method in which a peripheral circuit portion is formed of a LOCOS trench isolation layer, the LOCOS trench isolation layer is not formed around the transistor of the pixel portion and the light-receiving portion but a polycrystalline silicon oxide film is formed on the P+ region of the trench isolation region to thereby decrease stress and to decrease a dark current (see cited patent reference 2).    [Cited patent reference 1]: Official gazette of Japanese laid-open patent application No. 10-308507    [Cited patent reference 2:] Official gazette of Japanese laid-open patent application No. 11-312731
Accordingly, when the pixel portion uses the shallow trench isolation layer structure, in order to suppress the occurrence of the dark current on the side surface of the shallow trench isolation layer, it is sufficient that the P+ region may be formed around the shallow trench isolation layer.
FIG. 1 of the accompanying drawings is a schematic cross-sectional view showing a CMOS (complementary metal-oxide semiconductor) type solid-state image pickup device using a shallow trench isolation layer structure and a buried photodiode structure according to the related art.
A solid-state image pickup device, generally depicted by reference numeral 50 in FIG. 1, includes a substrate 51 on which a P-type semiconductor well region 52 is formed. An N-type semiconductor region 53 which serves as an electric charge accumulation region of a light-receiving sensor portion and an N− floating diffusion region 56 are formed on this P-type semiconductor well region 52.
Also, a P-type (P+) positive electric charge accumulation region 54 is formed near the surface of the substrate 51 on the N-type semiconductor region 53.
These P-type semiconductor well region 52, N-type semiconductor region 53 and P-type positive electric charge accumulation region 54 constitute a so-called buried photodiode structure.
Also, there is formed a shallow trench isolation layer 60 formed of an insulating layer (for example, a silicon oxide layer, a silicon nitride layer or a multilayer formed of the silicon oxide layer and the silicon nitride layer) for electrically isolating the transistor and the photodiode of the light-receiving sensor portion. The photodiode of the light-receiving sensor portion and the region such as the source/drain region of the transistor are formed near the substrate 51 in this shallow trench isolation layer 60.
The positive electric charge accumulation region 54 is formed adjacent to this shallow trench isolation layer 60 and it is formed wider than the N-type semiconductor region 53.
A gate insulating film 57 is formed on the surface of the substrate 51 and a read gate electrode 58 and a reset gate electrode 59 are formed on this gate insulating film 57.
The read gate electrode 58, the gate insulating film 57, the N-type semiconductor region 53 of the light-receiving sensor portion and the floating diffusion region 56 constitute a read transistor. A channel portion of this read transistor, that is, a space between the floating diffusion region 56 and the N-type semiconductor region 53 is formed as a read region 55.
Further, according to the need, assemblies such as a color filter or a on-chip lens are formed above to thereby construct the solid-state image pickup device 50.
Then, in this solid-state image pickup device 50, a P-type (P+) semiconductor region 61 is formed around (side wall and under) the shallow trench isolation layer 60. This P-type semiconductor region 61 can decrease a dark current generated around the shallow trench isolation layer 60.
However, in order to sufficiently suppress the occurrence of the dark current around the shallow trench isolation layer 60, the P-type semiconductor region 60 should be formed thick or a concentration of P-type impurities of the P-type semiconductor region 61 should be increased.
When the P-type semiconductor region 61 is formed thick, the area of the N-type semiconductor region 53 of the light-receiving sensor portion is decreased so that an amount of signal electric charges to be accumulated (amount of electric charges to be handled) also is decreased. Hence, it becomes difficult to main a desired dynamic range.
Further, when the concentration of the P-type impurities of the P-type semiconductor region 61 is increased, since the P-type impurities of the P-type semiconductor region 61 become easy to be diffused, the P-type impurities are easily diffused into the side of the light-receiving sensor portion. As a result, the amount of the signal electric charge that can be accumulated in the N-type semiconductor region 53 of the light-receiving sensor portion (amount of electric charges to be handled) is decreased unavoidably.
Further, this solid-state image pickup device 50 has the structure in which a contact hole of an interconnection is formed above the shallow trench isolation layer 60 as shown in FIG. 1.
That is, a contact portion gate electrode 62 is formed above the shallow trench isolation layer 60 through the gate insulating film 57, and this gate electrode 62 is connected to metal interconnections 64 of first and second layers through via interconnections 63 which connect the upper and lower metal interconnections 64.
Since this solid-state image pickup device 50 has the structure in which the contact hole of the interconnection 64 is formed above the shallow trench isolation layer 60 as described above, the solid-state image pickup device 50 is restricted from a pattern rule standpoint of the interconnection 64 and the contact hole. Further, considering a margin in the manufacturing process, it is necessary to maintain a width larger than a certain width of the shallow trench isolation layer 60.
Accordingly, it is frequently observed that the width of the shallow trench isolation layer 60 cannot be determined, and hence it becomes difficult to microminiaturize the device.
However, if the width of the shallow trench isolation layer 60 is increased, then also in this case, the area of the N-type semiconductor region 53 of the light-receiving sensor portion is decreased and the amount of signal electric charges that can be accumulated (amount of electric charges to be handled) also is decreased.
While the number of the pixels of the solid-state image pickup is increased and the solid-state image pickup device is microminiaturized increasingly or the power consumption of the solid-state image pickup device is decreased more increasingly in recent years, the pixel cell and the surrounding transistor should be microminiaturized and hence it becomes customary to use a shallow trench isolation layer as a device isolation structure of a transistor and the like.
On the other hand, in order to maintain an S/N (signal-to-noise ratio) and a sensitivity characteristic high enough as those of the camera, the solid-state image pickup device is requested to decrease a dark current more.
Accordingly, a buried photodiode structure which can suppress a dark current has so far been used as a structure of a light-receiving sensor portion.
However, as described above, when the buried photodiode and the shallow trench isolation layer are combined, there arises a problem in which the occurrence of the dark current in the side wall of the shallow trench isolation layer should be suppressed. When the P-type semiconductor region is formed on the side wall of the shallow trench isolation layer as a countermeasure for suppressing the occurrence of the dark current, there arises a secondary effect in which an amount of electric charges to be handled by the electric charge accumulation region is decreased unavoidably.